Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

An adaptive digital caliration of multi-step A/D converters.

A novel digital technique for efficient calibration of static errors in high-speed, high-resolution, multi-step ADCs is proposed. The parameter update within the calibration method is extended to include and correct effects of temperature and process variations. Additionally, to guide the verification process with the information obtained through monitoring process variations, expectation-maximization method is employed. The algorithm is evaluated on a prototype multi-step ADC converter with embedded dedicated sensors fabricated in standard single poly, six metal 0.09-樨 CMOS

Calibration and Debugging of Multi-step Analog to Digital Converters

This paper reports a new approach for debugging of the analog to digital converters based on process monitoring and extended design-for-test implementation. The circuit is re-configured in such a way that all sub-blocks are analysed and tested for their full input range allowing full observability and controllability of the analog to digital converter. To set initial data, estimate the parameter update and to guide the test, dedicated monitors have been designed. Additionally, the second presented algorithm allow circuit calibration without explicit need for any dedicated test signal nor requires a part of the conversion time. It works continuously and with every signal applied to the ADC

A real-time hybrid neuron network for highly parallel cognitive systems

For comprehensive understanding of how neurons communicate with each other, new tools need to be developed that can accurately mimic the behaviour of such neurons and neuron networks under 'real-time' constraints. In this paper, we propose an easily customisable, highly pipelined, neuron network design, which executes optimally scheduled floating-point operations for maximal amount of biophysically plausible neurons per FPGA family type. To reduce the required amount of resources without adverse effect on the calculation latency, a single exponent instance is used for multiple neuron calculation operations. Experimental results indicate that the proposed network design allows the simulation of up to 1188 neurons on Virtex7 (XC7VX550T) device in brain real-time yielding a speed-up of x12.4 compared to the state-of-the art

Regulatory Taking: A Contract Approach

This Article begins by defining the parameters of the fifth amendment\u27s taking clause. The Article then reviews the various tests used in determining whether governmental action constitutes a taking, and discusses the recent Supreme Court decisions within the framework of case law as it has evolved since the Court\u27s 1922 landmark decision, Pennsylvania Coal Co. v. Mahon. Finally, the Article suggests a formula based on well-established contract principles for analyzing the impact of land use regulation on private property interests

DfT for full accessibility of multi-step analog to digital converters.

This paper reports a Design for Testability (DfT) technique, which provides necessary diagnostic capability for signature-based and functional testing of multi-step analog to digital converters. The proposed approach permits circuit re-configuration in such a way that all sub-blocks are tested for their full input range allowing full observability and controllability of the device under test. The proposed DfT can be used for engineering pre-characterization as well, and can easily be interfaced to standards like I2C and IEEE 1149.1 TAP controllers. Experimental evidence is provided on the 12 bit multi-step analog to digital converter fabricated in standard single poly, six metal 0.09-mum CMOS

Analog automatic test pattern generation for quasi-static structural test.

A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability

An adaptive digital caliration of multi-step A/D converters.

A novel digital technique for efficient calibration of static errors in high-speed, high-resolution, multi-step ADCs is proposed. The parameter update within the calibration method is extended to include and correct effects of temperature and process variations. Additionally, to guide the verification process with the information obtained through monitoring process variations, expectation-maximization method is employed. The algorithm is evaluated on a prototype multi-step ADC converter with embedded dedicated sensors fabricated in standard single poly, six metal 0.09-樨 CMOS